The present invention relates to an output control circuit, more concretely, to an output control circuit using a bit map memory, and in particular, to an improvement of an output control circuit capable of effecting a high-speed processing of a dot pattern of a character in a frame buffer.
A memory control for achieving a raster display of output data on a computer graphic display has been described in the U.S. Pat. No. 4,197,590.
Heretofore, in character display apparatuses such as a computer system and a wordprocessor, often there has been adopted a code refresh method in which a location of each character is stored in a random access memory (RAM) so as to output a character pattern by use of a location in a character generator read-only memory (CGROM). Recently, a graphic display has been required in association with operations to display graphs and graphic images and the bit map refresh method is suitable for such graphic display. Incidentally, this also applies to the printer apparatus of a laser beam printer (LBP) for printing data in which characters, graphics, and image information are mixed.
According to the bit map refresh method, however, in the output or printing operation, the character output or print position supplied in the form of a logical address of X and Y coordinates must undergo an address conversion to attain a physical address of a frame buffer constituted with a bit map memory and moreover a bit shift processing must be effected to develop the dot patterns of characters in the frame buffer. As a result, when compared with the output method of the conventional code refresh method, the bit map refresh method has the disadvantage that the output processing speed is low. Incidentally, bit pattern shift processing is required in a case where a central processing unit (CPU) reads data from a character generator ROM (CGROM) storing the dot patterns of characters so as to write the data in a frame buffer. Namely, in general, the word boundary of the data stored in the CGROM does not match that of the frame buffer; consequently, when writing data in the frame buffer, the write data must be aligned with the word boundary of the frame buffer. This causes the output processing speed to be reduced. To overcome this difficulty, an article by M. Ishihara et al., entitled "256K Image Dual Port Memory Having Raster Operation Function and Serial Input Function"; Nikkei Electronics, Nikkei McGraw-Hill, Mar. 24, 1986, pp. 243-264 has proposed a method in which a high-speed development is accomplished with hardware.
Furthermore, conventionally, for the addresses and data of the frame buffer, the data of a memory device is assigned in one of the X-axis and Y-axis directions for X and Y coordinates as shown in FIG. 5 and the addresses of the memory device are assigned in the direction of the other axis. In this situation, when accessing a row of data in a direction of an axis, since n (eight in FIG. 5) memory devices correspond to the respective data terminals, the data can be simultaneously accessed. However, in a case of accessing a row of data in the direction of the other axis, since a memory device having a data terminal corresponds to n data items, the simultaneous access cannot be effected. Consequently, an operation to access the frame buffer is possible only in one direction. On the other hand, in a case where data is stored to be directed to a fixed direction with respect to the CGROM generating the dot patterns of characters, when the CPU reads data from the CGROM and writes the data in the frame buffer, the output character is directed in a predetermined direction. As a result, even when the character is desired to be directed in the horizontal or vertical direction, only the output character directed in the predetermined direction can be displayed at a high speed directly. For the higher speed, to meet the requirements above, the dot patterns of characters undergo a bit pattern conversion through software processing; however, the conversion processing cannot be achieved at a satisfactory high speed. To overcome this problem, the Japanese Patent Laid-Open No. 60-200285 (JP-A-60-200285) has proposed a method in which the bit pattern conversion is hardwarewise implemented in the form of a matrix so as to increase the speed of the bit layout conversion processing
However, in a case where the bit shift processing of the character dot pattern is accomplished by means of a hardware system, when a character position supplied in the form of a logical address including X and Y coordinates is developed as a physical address of the frame buffer in the conventional method, since the address conversion is not supported by the hardware system, the address conversion processing must be achieved by a software processing, which increases the processing load imposed on the CPU. Moreover, in the case of bit shift processing where, for example, 7-bit source data is shifted by three bits so as to be eight bits, the bit width of the data actually written in the frame buffer is EQU 8 bits-3 bits=5 bits
The two remaining bits not written in the write processing above undergo a write processing so as to be written in a word at an address adjacent to the preceding address word in the frame buffer. In the prior art technology, however, the software first checks to determine whether the write data bridges a word boundary of the frame buffer, and if this is the case, the remaining data not written is written at the subsequent address through software processing, which leads to a problem to be solved to effect the output processing at a higher speed.
In addition, when the processing to convert the bit layout of the character dot pattern is achieved in the prior art technology, a bit layout converter is required, and in the CPU processing in this case, the data read from the CGROM is first transferred to the bit layout converter and the transferred data is thereafter developed in the frame buffer, namely, as compared with a case where the data of the CGROM is directly developed in the frame buffer, there arises a problem that the processing speed is lowered.